CRPE211 Week 10 Notes: How does interrupt work?

Zhao Zhang
March 22, 2006.

1.      Why the execution of a program can be interrupted and resumed?

A program execution is interruptible because the program execution on a computer is fundamentally an execution of a finite state machine (a really big one). If an execution phase does not involve I/O, then the execution is totally determined by the states of the machine, as the following figure shows:

Here Si is the machine state of the program execution after the i-th instruction, and Ii is the i-th instruction. In other words, the program execution can be viewed as a transition of finite state machine from S0 to Sn. The machine state, precisely, is the register and memory contents involved in the program execution. The register states are those of all registers; in PowerPC, they include the general-purpose registers (r0-r31), PC (program counter), CR, XER, LR and others. Before the program accesses I/O ports, the execution is pre-determined, i.e. S0 determines S1, S1 determines S2, and so on. (Why is that?)

Q: Which machine state does a branch instruction change?
A: The PC register.

Because of this property of program execution, a program execution can be stopped and resumed at any step by restoring the machine state. For example, if an interrupt happens after the completion of the k-th instruction, the program execution can be altered as following:

S’0 and S’n are the start and finish states of the execution of the interrupt handler. The machine state Sk+1 is saved before the interrupt handler starts execution, and restored after the interrupt handler finishes. Then the original program execution is restored as if nothing happened.

Q: Should the non-volatile registers be saved if the interrupt handler is going to change them?
A: Yes. All register values, if they are to be changed, must be saved and restored. Those include r0-r31, CR, XER, LR and PC and more.

2.      What is the difference between exception and interrupt, and how the handlers are found?

The interrupt mechanism as described above can be used for interrupt events from I/O devices. However, it also works fine for handling other exceptional events from the CPU; for example, memory violation and address misalignment. In PowerPC terms, all those events are called exceptions; and the external interrupt events from I/O devices are called external interrupt exceptions. In other words, I/O interrupts become a subclass of exception.

Interrupt or exception makes a big difference in designing the interrupt logic of a pipeline processor. However, they do not make much difference from a programmer’s viewpoint. Each type of exception is handled by an exception handler; in PowerPC terms, exception service routine (ESR). Thus, there is an external interrupt ESR corresponding to all the external I/O interrupts (except a special case). The addresses of all ESRs are hardware-wired in the MPC555 processor; and the system programmer must put the code of those ESRs at the right addresses.

Since all I/O events go through the external interrupt ESR, how does it get to know which I/O device is raising the interrupt? In MPC555 there is an interrupt controller which collects all interrupt signals from the I/O devices and sends an exception signal to the CPU. It has an encoding logic to generate an interrupt code. The code is stored into a memory-mapped register of the interrupt controller, and the ESR can read that register. The ESR should maintain a table of the starting addresses of all ISRs in its own memory. Then the ESR can use the interrupt code as an address to access the ISR table, get the ISR address, and jump to the starting address of the ISR.

3.      Who should save and restore the machine states, hardware or software?

Both. The external interrupt ESR can save almost all registers into stack, get the interrupt code and call the corresponding ISR, and then restore the register contents. However, there are a few registers that will be changed before the ESR is executed. Firstly, the CPU forces a jump to the ESR by setting the PC to the starting address of the ESR. Thus, the original PC value has changed before the ESR starts the execution. In PowerPC, the CPU saves the original PC into a special register upon an interrupt. The ESR is responsible to save and restore the value of that special register. Secondly, there is another special register that must be handled in a similar way, which you will see next week.